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參數(shù)資料
| 型號： | P87C770 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)(在NTSC TV中應(yīng)用的具有屏幕顯示和字幕關(guān)閉特點的微控制器) |
| 中文描述： | 微控制器用于NTSC電視的屏幕顯示（OSD）和字幕（CC）的（在NTSC電視中應(yīng)用的具有屏幕顯示和字幕關(guān)閉特點的微控制器） |
| 文件頁數(shù)： | 26/80頁 |
| 文件大?。?/td> | 266K |
| 代理商： | P87C770 |
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1999 Jun 11
26
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
P8xCx70 family
12 OSCILLATOR CIRCUITRY
The on-chip oscillator circuitry of the P8xCx70 is a
single-stage inverting amplifier biased by an internal
feedback resistor. For operation as a standard quartz
oscillator or when using an external ceramic resonator,
external components are needed and should be
connected as shown in Fig.8.
In the Power-down mode the oscillator is stopped and both
XI and XO are pulled HIGH. The inverting amplifier and
feedback resistor are both switched off to ensure no
current will flow regardless of the voltages at XI and XO.
To drive the device with an external clock source, apply the
external clock signal to XI, and leave XO to float. There is
no requirement on the duty cycle of the external clock,
because the external clock is divided-by-two using a
flip-flop before feeding the internal clocking circuitry.
The operating frequency of crystal oscillator is fixed at
12 MHz.
13 RESET
There are three ways to invoke a reset and initialize the
P8xCx70:
Via the external RESET pin
Via the on-chip Power-on reset circuitry
Via a Watchdog Timer overflow.
Fig.8 Oscillator configuration.
For quartz crystal or ceramic resonator.
handbook, halfpage
MBE311
XI
XO
The reset mechanism is illustrated in Fig.9. Each reset
source will cause the internal reset signal POC to become
active. The CPU responds by executing an internal reset
putting the internal registers into a defined state as
detailed in Table 34.
13.1
External reset
The reset pin RESET is connected to a Schmitt trigger for
noise reduction (see Fig.9). A reset is accomplished by
holding the RESET pin HIGH for at least 2 machine cycles
(24 system clocks), while the oscillator is running.
If the RESET pin is connected to V
DD
via a capacitor as
shown in Fig.9, an automatic reset can be obtained by
switching on V
DD
, The V
DD
rise time must not exceed
10 ms and the capacitor should be at least 10
μ
F.
The decrease of the RESET pin voltage depends on the
capacitor and the internal resistor R
RESET
. The voltage
must remain above the lower threshold level for a
minimum period determined by the oscillator start-up time
plus 2 machine cycles. For the P8xCx70 an external
capacitor value of 10
μ
F is needed.
13.2
Power-on reset
An on-chip Power-on reset circuit detects supply voltage
variations and generates a Power-on reset pulse
accordingly; see Fig.10.
In the case of supply voltage ramp-up, the power-on reset
signal follows the ramp-up of the supply voltage. When the
trip level (V
t
) is reached, the power-on reset signal will be
maintained for a time period (T
p
) before reverting back to
its LOW state.
In the case of supply voltage drop, after the trip level (V
t
) is
reached, the power-on reset signal will respond within T
r
.
The internal reset will remain active until T
p
after the V
t
has
been exceeded.
The time interval (T
p
) is used to guarantee a complete
power-on reset pulse so that this signal can trigger the
internal reset signal. However, to ensure the oscillator is
stable before the controller starts, the clock is gated away
from the CPU for a further 2048 oscillator cycles.
13.3
Watchdog Timer overflow
The length of the output pulse from T3 is 3 machine cycles.
A pulse of such short duration is necessary in order to
recover from a processor or system fault as fast as
possible.
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