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參數(shù)資料
| 型號： | P87C770AAR |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52 |
| 文件頁數(shù)： | 51/80頁 |
| 文件大?。?/td> | 266K |
| 代理商： | P87C770AAR |
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1999 Jun 11
51
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
P8xCx70 family
18.8
General controls
18.8.1
P
OLARITY OF
HSYNC
AND
VSYNC
INPUT SIGNALS
The horizontal and vertical input sync signals can be
inverted by setting the HPOL and VPOL bits in the Text
Vertical Position Register (see Section 18.9.2).
Table 74
Sync signal polarity
18.8.2
F
RAME RESET GENERATION
Normally, VSYNC of the first field occurs during the first
half line period and Vsync of the second field occurs during
the second half period of a scan-line. In this case it is very
easy to generate a frame reset signal. The VSYNC pulse
is generated by sampling and rising edge detection.
HPOL
VPOL
SYNC SIGNAL POLARITY
0
1
0
1
input polarity
input inverted polarity
These VSYNC pulses are gated (AND gate) with a line
frequency signal which has a duty cycle of 50 : 50 (H50).
The output signal is the frame reset pulse. The rising edge
of the H50 signal is generated from the HSYNC pulse.
The falling edge is generated via a comparison between
the fixed value of half of the nominal number of 768 pixels
per line (comparator value: 384 pixels) and the value of a
pixel counter.
If the VSYNC of one field occurs shortly after the falling
edge of H50 and the line period has more than the nominal
number of 768 pixels per line, it is possible that both
VSYNC pulses occur during the low period of H50.
The result is that no frame reset pulse is generated. In the
case of a VSYNC pulse occurring shortly after the rising
edge of H50 and less than the nominal number of
768 pixels per line it is possible that every VSYNC pulse
will generate a frame reset pulse. To prevent this
happening the position of H50 is adjustable in increments
of 12 clock cycles. The adjustment value is selected using
the Odd/Even Align Register.
Fig.22 Frame reset timing.
handbook, full pagewidth
MGL151
Hsync
Frame
reset
H50
Vsync_In
Vsync
(sampled)
Hsync
Frame
reset
Field 2
H50
Vsync_In
Vsync
(sampled)
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