參數(shù)資料
型號： P89C662
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-Bit Flash Microcontroller 32KB ISP/IAP FLASH with 1KB RAM(80C51 8位閃速微控制器，帶16KB ISP/IAP閃速存儲器和1KB RAM)
中文描述： 80C51的8位閃存微控制器具有32KB的ISP /聯(lián)合會與1kB的內(nèi)存（80C51的8位閃速微控制器，帶16KB的供應(yīng)商/聯(lián)合會閃速存儲器和閃存的1kB的RAM）
文件頁數(shù)： 28/89頁
文件大?。?/td> 490K
代理商： P89C662
Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
28
Table 6.
Slave Receiver mode
(Continued)
STATUS
CODE
(S1STA)
STATUS OF THE
I
2
C BUS AND
SIO1 HARDWARE
APPLICATION SOFTWARE RESPONSE
TO/FROM S1DAT
TO S1CON
NEXT ACTION TAKEN BY SIO1 HARDWARE
STA
STO
SI
AA
A0H
A STOP condition or
repeated START
di i
condition has b
received while still
addressed as
SLV/REC or SLV/TRX
No STDAT action or
0
0
0
0
Switched to not addressed SLV mode; no recognition
of own SLA or General call address
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes
free
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1. A START condition
will be transmitted when the bus becomes free.
No STDAT action or
0
0
0
1
No STDAT action or
1
0
0
0
No STDAT action
1
0
0
1
Table 7.
Slave Transmitter mode
STATUS
CODE
(S1STA)
STATUS OF THE
I
2
C BUS AND
SIO1 HARDWARE
APPLICATION SOFTWARE RESPONSE
TO/FROM S1DAT
TO S1CON
NEXT ACTION TAKEN BY SIO1 HARDWARE
STA
STO
SI
AA
A8H
Own SLA+R has
been received; ACK
has been returned
Load data byte or
X
0
0
0
Last data byte will be transmitted and ACK bit will be
received
Data byte will be transmitted; ACK will be received
load data byte
X
0
0
1
B0H
Arbitration lost in
SLA+R/W as master;
Own SLA+R has
been received, ACK
has been returned
Load data byte or
X
0
0
0
Last data byte will be transmitted and ACK bit will be
received
load data byte
X
0
0
1
Data byte will be transmitted; ACK bit will be received
B8H
Data byte in S1DAT
has been transmitted;
ACK has been
received
Load data byte or
X
0
0
0
Last data byte will be transmitted and ACK bit will be
received
load data byte
X
0
0
1
Data byte will be transmitted; ACK bit will be received
C0H
Data byte in S1DAT
has been transmitted;
NOT ACK has b
received
No S1DAT action or
0
0
0
01
Switched to not addressed SLV mode; no recognition
of own SLA or General call address
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes
free
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1. A START condition
will be transmitted when the bus becomes free.
no S1DAT action or
0
0
0
1
no S1DAT action or
1
0
0
0
no S1DAT action
1
0
0
1
C8H
Last data byte in
S1DAT has been
transmitted (AA
ACK has been
received
0)
No S1DAT action or
0
0
0
0
Switched to not addressed SLV mode; no recognition
of own SLA or General call address
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes
free
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be
recognized if S1ADR.0 = logic 1. A START condition
will be transmitted when the bus becomes free.
no S1DAT action or
0
0
0
1
no S1DAT action or
1
0
0
0
no S1DAT action
1
0
0
1
相關(guān)PDF資料
PDF描述
P89C668HBA 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
P89C668HFA 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
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參數(shù)描述
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