參數(shù)資料
型號： P89C662
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-Bit Flash Microcontroller 32KB ISP/IAP FLASH with 1KB RAM(80C51 8位閃速微控制器，帶16KB ISP/IAP閃速存儲器和1KB RAM)
中文描述： 80C51的8位閃存微控制器具有32KB的ISP /聯(lián)合會與1kB的內(nèi)存（80C51的8位閃速微控制器，帶16KB的供應(yīng)商/聯(lián)合會閃速存儲器和閃存的1kB的RAM）
文件頁數(shù)： 62/89頁
文件大?。?/td> 490K
代理商： P89C662
Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
62
ERAM
256, 768,
1792 OR 7936
BYTES
UPPER
128 BYTES
INTERNAL RAM
LOWER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
000
FF
00
FF
00
80
80
EXTERNAL
DATA
MEMORY
FFFF
0000
SU01712
FF/2FF/6FF/1FFF
Figure 54. Internal and External Data Memory Address Space with EXTRAM = 0
Hardware WatchDog Timer (One-Time Enabled
with Reset-Out for P89C660/662/664/668)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, user must write 01EH
and 0E1H in sequence to the WDTRST (SFR location 0A6H). When
WDT is enabled, it will increment every machine cycle while the
oscillator is running and there is no way to disable the WDT except
through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output reset HIGH pulse at the RST
pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to
the WDTRST (SFR location 0A6H). When WDT is enabled, the user
needs to service it by writing 01EH and 0E1H to WDTRST to avoid
WDT overflow. The 14-bit counter overflows when it reaches 16383
(3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This
means the user must reset the WDT at least every 16383 machine
cycles. To reset the WDT, the user must write 01EH and 0E1H to
WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When the WDT overflows, it will generate
an output RESET pulse at the RST pin. The RESET pulse duration
is 98
×
T
OSC
(6 clock mode; 196 in 12 clock mode), where
T
OSC
= 1/f
OSC
. To make the best use of the WDT, it should be
serviced in those sections of code that will periodically be executed
within the time required to prevent a WDT reset.
相關(guān)PDF資料
PDF描述
P89C668HBA 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
P89C668HFA 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
P89C668 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
P89C668HBBD 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
P89CE558 Single-chip 8-bit microcontroller(8位單片微控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P89C662HBA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family
P89C662HBA/00,512 功能描述:IC 80C51 MCU FLASH 32K 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:89C 產(chǎn)品培訓(xùn)模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標(biāo)準(zhǔn)包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲器容量:192KB（96K x 16） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 16x12b; D/A 2x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
P89C662HBBD 制造商: 功能描述: 制造商:undefined 功能描述:
P89C662HBBD/00,557 制造商:NXP Semiconductors 功能描述:
P89C662HFA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family
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