參數(shù)資料
型號: P89LPC9102FTK,115
廠商: NXP Semiconductors
文件頁數(shù): 14/39頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 1K 10-HVSON
標準包裝: 1
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 1KB(1K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-VFDFN 裸露焊盤
包裝: 標準包裝
配用: 622-1006-ND - SOCKET ADAPTER BOARD
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-2000-6
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P89LPC9102_9103_9107_3
NXP
B
.V
.2007.
All
r
ights
reser
v
ed.
Pr
oduct
data
sheet
Re
v
.03
10
J
u
ly
2007
21
of
61
NXP
Semiconductor
s
P89LPC9102/9103/9107
8-bit
micr
ocontr
oller
s
with
tw
o-c
loc
k
accelerated
80C51
core
[1]
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specied, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
[2]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
Bit address
D7
D6
D5
D4
D3
D2
D1
D0
PSW*
Program status word
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
00
0000 0000
PT0AD
Port 0 digital input disable
F6H
-
PT0AD.5
PT0AD.4
PT0AD.3
PT0AD.2
PT0AD.1
-
00
xx00 000x
RSTSRC
Reset source register
DFH
-
BOF
POF
R_BK
R_WD
R_SF
R_EX
RTCCON
Real-time clock control
D1H
RTCF
RTCS1
RTCS0
-
ERTC
RTCEN
011x xx00
RTCH
Real-time clock register high
D2H
0000 0000
RTCL
Real-time clock register low
D3H
0000 0000
SADDR
Serial port address register
A9H
00
0000 0000
SADEN
Serial port address enable
B9H
00
0000 0000
SBUF
Serial port data buffer register
99H
xx
xxxx xxxx
Bit address
9F
9E
9D
9C
9B
9A
99
98
SCON*
Serial port control
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
00
0000 0000
SSTAT
Serial port extended status
register
BAH
DBMOD
INTLO
CIDIS
DBISEL
FE
BR
OE
STINT
00
0000 0000
SP
Stack pointer
81H
07
0000 0111
Bit address
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer 0 and 1 control
88H
TF1
TR1
TF0
TR0
----
00
0000 0000
TH0
Timer 0 high
8CH
00
0000 0000
TH1
Timer 1 high
8DH
00
0000 0000
TL0
Timer 0 low
8AH
00
0000 0000
TL1
Timer 1 low
8BH
00
0000 0000
TMOD
Timer 0 and 1 mode
89H
-
T1M1
T1M0
-
T0M1
T0M0
00
0000 0000
TRIM
Internal oscillator trim register
96H
RCCLK
-
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
Table 8.
P89LPC9103 special function registers …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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