參數(shù)資料
型號: P89LPC9102FTK,115
廠商: NXP Semiconductors
文件頁數(shù): 25/39頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 1K 10-HVSON
標(biāo)準(zhǔn)包裝: 1
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲(chǔ)器容量: 1KB(1K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-VFDFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
配用: 622-1006-ND - SOCKET ADAPTER BOARD
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-2000-6
P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
31 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.12 I/O ports
The P89LPC9102/9103/9107 has either 6, 7, or 8 I/O pins depending on the reset pin
option and clock source option chosen. Refer to Table 10.
[1]
Required for operation above 12 MHz.
8.12.1 Port congurations
All but one I/O port pin on the P89LPC9102/9103/9107 may be congured by software to
one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two conguration registers for each port
select the output type for each port pin.
P1.5 (RST) can only be an input and cannot be congured.
Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9103/9107)
002aaa977
BOF
EBO
KBIF
EKBI
interrupt
to CPU
wake-up
(if in power-down)
EWDRT
CMF
EC
EA (IE0.7)
RTCF
ERTC
(RTCCON.1)
WDOVF
TF1
ET1
TI and RI/RI
ES/ESR
TI
EST
TF0
ET0
ENADCI1
ADCI1
ENBI1
BNDI1
EAD
Table 10.
Number of I/O pins available
Clock source
Reset option
Number of I/O pins
(10-pin package)
Number of I/O pins
(14-pin package)
On-chip oscillator or watchdog
oscillator
No external reset (except during
power-up)
810
External RST pin supported
7
9
External clock input
No external reset (except during
power-up)
79
External RST pin supported[1]
68
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