參數(shù)資料
型號: P89LPC913
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
中文描述: 8位微控制器兩個小時80C51的核心具有1KB 3伏閃光的128字節(jié)RAM
文件頁數(shù): 26/63頁
文件大?。?/td> 314K
代理商: P89LPC913
Philips Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 03 — 17 December 2004
26 of 63
9397 750 14468
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.
Functional description
Remark:
Please refer to the P89LPC912/913/914 User’s Manualfor a more detailed
functional description.
9.1 Enhanced CPU
The P89LPC912/913/914 uses an enhanced 80C51 CPU which runs at 6 times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles,
and most instructions execute in one or two machine cycles.
9.2 Clocks
9.2.1
Clock definitions
The P89LPC912/913/914 device has several internal clocks as defined below:
OSCCLK —
Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see
Figure 10
,
11
, and
12
) and can also be optionally divided to a
slower frequency (see
Section 9.7 “CPU Clock (CCLK) modification: DIVM register”
).
Note:
f
osc
is defined as the OSCCLK frequency.
CCLK —
CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).
RCCLK —
The internal 7.373 MHz RC oscillator output.
PCLK —
Clock for the various peripheral devices and is CCLK/2
9.2.2
CPU clock (OSCCLK)
The P89LPC912/913/914 provide user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the FLASH is programmed and
include an on-chip Watchdog oscillator and an on-chip RC oscillator.
In addition, both the P89LPC912 and P89LPC913 provide an oscillator using an
external crystal or an external clock source. The crystal oscillator can be optimized
for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.
9.2.3
Low speed oscillator option (P89LPC912, P89LPC913)
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
9.2.4
Medium speed oscillator option (P89LPC912, P89LPC913)
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
9.2.5
High speed oscillator option (P89LPC912, P89LPC913)
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration.
When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until V
DD
has
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