參數(shù)資料
型號(hào): P89LPC9151FDH,129
廠商: NXP Semiconductors
文件頁數(shù): 23/27頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 2KB 14TSSOP
標(biāo)準(zhǔn)包裝: 96
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲(chǔ)器容量: 2KB(2K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b; D/A 1x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 568-8738-5
935290259129
P89LPC9151FDH,129-ND
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 87
PIC18F87J72 FAMILY
8.0
8 x 8 HARDWARE MULTIPLIER
8.1
Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
8.2
Operation
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
EXAMPLE 8-1:
8 x 8 UNSIGNED MULTIPLY
ROUTINE
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 8-1:
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF
ARG1, W
;
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF
ARG1, W
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC
ARG2, SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
;
- ARG1
MOVF
ARG2, W
BTFSC
ARG1, SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
;
- ARG2
Routine
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 48 MHz
@ 10 MHz
@ 4 MHz
8 x 8 unsigned
Without hardware multiply
13
69
5.7
s27.6 s69 s
Hardware multiply
1
83.3 ns
400 ns
1
s
8 x 8 signed
Without hardware multiply
33
91
7.5
s36.4 s91 s
Hardware multiply
6
500 ns
2.4
s6 s
16 x 16 unsigned
Without hardware multiply
21
242
20.1
s96.8 s242 s
Hardware multiply
28
2.3
s
11.2
s28 s
16 x 16 signed
Without hardware multiply
52
254
21.6
s
102.6
s254 s
Hardware multiply
35
40
3.3
s16.0 s40 s
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