參數(shù)資料
型號(hào): P89LPC9221FDH,512
廠商: NXP Semiconductors
文件頁(yè)數(shù): 18/46頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 75
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
包裝: 管件
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1010-ND - BOARD FOR LPC922 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-3223-5
935278674512
P89LPC9221FDH
Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 08 — 15 December 2004
25 of 46
9397 750 14469
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.18.2
Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical ‘0’), 8 data bits (LSB rst), and a stop bit (logical ‘1’). When data is received,
the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is
variable and is determined by the Timer 1 overow rate or the Baud Rate Generator
8.18.3
Mode 2
11 bits are transmitted (through TxD) or received (through RxD): start bit (logical ‘0’),
8 data bits (LSB rst), a programmable 9th data bit, and a stop bit (logical ‘1’). When
data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of ‘0’ or
‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When
data is received, the 9th data bit goes into RB8 in Special Function Register SCON,
while the stop bit is not saved. The baud rate is programmable to either 1
16 or 132 of
the CPU clock frequency, as determined by the SMOD1 bit in PCON.
8.18.4
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical ‘0’), 8 data bits (LSB rst), a programmable 9th data bit, and a stop bit
(logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable and is determined by the Timer 1 overow rate or
the Baud Rate Generator (described in Section 8.18.5 “Baud rate generator and
8.18.5
Baud rate generator and selection
The P89LPC920/921/922/9221 enhanced UART has an independent Baud Rate
Generator. The baud rate is determined by a baud-rate preprogrammed into the
BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that
works in a similar manner as Timer 1 but is much more accurate. If the baud rate
generator is used, Timer 1 can be used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 7).
Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is set. The
independent Baud Rate Generator uses OSCCLK.
8.18.6
Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If
SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is ‘0’.
Fig 7.
Baud rate sources for UART (Modes 1, 3).
Baud Rate Modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
2
Timer 1 Overflow
(PCLK-based)
Baud Rate Generator
(CCLK-based)
002aaa419
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