參數(shù)資料
型號(hào): P89LPC9221FDH,512
廠商: NXP Semiconductors
文件頁數(shù): 32/46頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 75
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
包裝: 管件
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1010-ND - BOARD FOR LPC922 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-3223-5
935278674512
P89LPC9221FDH
Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 08 — 15 December 2004
38 of 46
9397 750 14469
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11. Dynamic characteristics
[1]
Parameters are valid over operating temperature range unless otherwise specied. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
Table 9:
AC characteristics
VDD = 2.4 V to 3.6 V unless otherwise specied.
Tamb = 40 °Cto+85 °C for industrial, unless otherwise specied.[1]
Symbol
Parameter
Conditions
Variable clock
fosc =12MHz
Unit
Min
Max
Min
Max
fRCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz)
trimmed to
±1%
at Tamb =25 °C
7.189
7.557
7.189
7.557
MHz
fWDOSC
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
320
520
320
520
kHz
fosc
oscillator frequency
0
12
-
MHz
tCLCL
clock cycle
83
-
ns
fCLKP
CLKLP active frequency
0
8
-
MHz
Glitch lter
glitch rejection, P1.5/RST pin
-
50
-
50
ns
signal acceptance, P1.5/RST pin
125
-
125
-
ns
glitch rejection, any pin except
P1.5/RST
-
15
-
15
ns
signal acceptance, any pin except
P1.5/RST
50
-
50
-
ns
External clock
tCHCX
HIGH time
33
tCLCL tCLCX
33
-
ns
tCLCX
LOW time
33
tCLCL tCHCX
33
-
ns
tCLCH
rise time
-8
-
8
ns
tCHCL
fall time
-8
-
8
ns
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
16 tCLCL
-
1333
-
ns
tQVXH
output data set-up to clock rising
edge
13 tCLCL
-
1083
-
ns
tXHQX
output data hold after clock rising
edge
-tCLCL + 20
-
103
ns
tXHDX
input data hold after clock rising edge
-
0
-
0
ns
tDVXH
input data valid to clock rising edge
150
-
150
-
ns
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