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參數(shù)資料
| 型號： | P89LPC9321FDH,512 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 40/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU 8KB FLASH 28TSSOP |
| 標準包裝： | 51 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 管件 |
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P89LPC9321
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 16 November 2010
45 of 71
NXP Semiconductors
P89LPC9321
8-bit microcontroller with accelerated two-clock 80C51 core
7.29 Additional features
7.29.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
7.29.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects one of
the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS
bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1
register, without the possibility of inadvertently altering other bits in the register.
7.29.3 Data EEPROM
The P89LPC9321 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR
based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can
read, write and fill the memory via SFRs and one interrupt. This Data EEPROM provides
100,000 minimum erase/program cycles for each byte.
Byte mode: In this mode, data can be read and written one byte at a time.
Row fill: In this mode, the addressed row (64 bytes) is filled with a single value. The
entire row can be erased by writing 00H.
Sector fill: In this mode, all 512 bytes are filled with a single value. The entire sector
can be erased by writing 00H.
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed
sequence.
Fig 20. Watchdog timer in Watchdog mode (WDTE = 1)
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDCON (A7H)
SHADOW REGISTER
PRESCALER
002aae015
8-BIT DOWN
COUNTER
WDL (C1H)
watchdog
oscillator
crystal
oscillator
PCLK
XTALWD
÷32
0
1
0
1
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
reset(1)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC9321FN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM |
| P89LPC9321FN,112 | 功能描述:8位微控制器 -MCU Enhanced LPC932A1 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC932A1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-Bit Microcontroller with accelerated two-clock 80C51 core 8kB 3V byte-erasable flash with 512-byte data EEPROM |
| P89LPC932A1FA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-Bit Microcontroller with accelerated two-clock 80C51 core 8kB 3V byte-erasable flash with 512-byte data EEPROM |
| P89LPC932A1FA,112 | 功能描述:8位微控制器 -MCU 8K FL/768B RAM/512B EE/CCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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