參數(shù)資料
型號(hào)： P89LPC9351FA,529
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 2/94頁(yè)
文件大小： 0K
描述： IC 80C51 MCU FLASH 8K 28-PLCC
標(biāo)準(zhǔn)包裝： 37
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 26
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b; D/A 2x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-PLCC
包裝： 管件
配用： 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱： 935287627529
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
10 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
P2.0 to P2.7
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0/ICB/DAC0
/AD03
1I/O
P2.0 — Port 2 bit 0.
I
ICB — Input Capture B. (P89LPC9351/9361)
O
DAC0 — Digital-to-analog converter output.
I
AD03 — ADC0 channel 3 analog input.
P2.1/OCD/AD02
2
I/O
P2.1 — Port 2 bit 1.
O
OCD — Output Compare D. (P89LPC9351/9361)
I
AD02 — ADC0 channel 2 analog input.
P2.2/MOSI
13
I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input.
P2.3/MISO
14
I/O
P2.3 — Port 2 bit 3.
I/O
MISO — When configured as master, this pin is input, when configured as slave,
this pin is output.
P2.4/SS
15
I/O
P2.4 — Port 2 bit 4.
I
SS — SPI Slave select.
P2.5/SPICLK
16
I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6/OCA
27
I/O
P2.6 — Port 2 bit 6.
O
OCA — Output Compare A. (P89LPC9351/9361)
P2.7/ICA
28
I/O
P2.7 — Port 2 bit 7.
I
ICA — Input Capture A. (P89LPC9351/9361)
P3.0 to P3.1
I/O
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
All pins have Schmitt trigger inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT
9I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the flash configuration.
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).
It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the RTC/system timer.
Table 3.
Pin description …continued
Symbol
Pin
Type Description
PLCC28,
TSSOP28
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