參數(shù)資料
型號(hào): P89LPC9351FA,529
廠商: NXP Semiconductors
文件頁(yè)數(shù): 25/94頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28-PLCC
標(biāo)準(zhǔn)包裝: 37
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b; D/A 2x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-PLCC
包裝: 管件
配用: 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 935287627529
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
31 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.5 Clock output
The P89LPC9331/9341/9351/9361 supports a user-selectable clock output function on
the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator
as their clock source. This allows external devices to synchronize to the
P89LPC9331/9341/9351/9361. This output is enabled by the ENCLK bit in the TRIM
register.
The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.6 On-chip RC oscillator option
The P89LPC9331/9341/9351/9361 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
preprogrammed value to adjust the oscillator frequency to 7.373 MHz
1 % at room
temperature. End-user applications can write to the TRIM register to adjust the on-chip
RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG2.7 =
1), the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5)
and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD
has reached its specified level.
7.7 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to
5 % at room temperature. This oscillator can be used to save power when a high clock
frequency is not needed.
7.8 External clock input option
In this configuration, the processor clock is derived from an external source driving the
P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be
used as a standard port pin or a clock output. When using an oscillator frequency above
12 MHz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in
reset at power-up until VDD has reached its specified level.
7.9 Clock source switching on the fly
P89LPC9331/9341/9351/9361 can implement clock switching on any sources of
watchdog oscillator, 7 MHz/14 MHz internal RC oscillator, crystal oscillator and external
clock input during code is running. CLKOK bit in CLKCON register is used to indicate the
clock switch status. CLKOK is cleared when starting clock source switch and set when
completed. Notice that when CLKOK is ‘0’, writing to CLKCON register is not allowed.
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