參數(shù)資料
型號: P89LPC938FA,129
廠商: NXP Semiconductors
文件頁數(shù): 49/68頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28-PLCC
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 37
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-LCC(J 形引線)
包裝: 管件
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1011-ND - BOARD FOR LPC938 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-2252-5
935278545129
P89LPC938FA-S
2010 Microchip Technology Inc.
DS39933D-page 53
PIC18F87J90 FAMILY
5.0
RESET
The PIC18F87J90 family of devices differentiates
between various kinds of Reset:
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Brown-out Reset (BOR)
Configuration Mismatch (CM) Reset
RESET Instruction
Stack Full Reset
Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
WDT Resets are covered in Section 25.2 “Watchdog
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External Reset
MCLR
VDD
WDT
Time-out
VDD Rise
Detect
PWRT
INTRC
POR Pulse
PWRT
Chip_Reset
11-Bit Ripple Counter
Brown-out
Reset(1)
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
IDLE
65.5 ms (typical)
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
Configuration Word
Mismatch
32
s (typical)
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