參數(shù)資料
型號: P89LPC938FA,129
廠商: NXP Semiconductors
文件頁數(shù): 52/68頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 28-PLCC
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 37
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-LCC(J 形引線)
包裝: 管件
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1011-ND - BOARD FOR LPC938 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-2252-5
935278545129
P89LPC938FA-S
PIC18F87J90 FAMILY
DS39933D-page 56
2010 Microchip Technology Inc.
5.6
Power-up Timer (PWRT)
PIC18F87J90 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F87J90 fam-
ily devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32
s = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 for details.
5.6.1
TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 5-3, Figure 5-4,
and
all
depict
time-out
sequences on power-up with the Power-up Timer
enabled.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR
high
will
begin
execution
immediately
(Figure 5-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
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