參數(shù)資料
型號: P89LPC9401FBD,557
廠商: NXP Semiconductors
文件頁數(shù): 12/59頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 64-LQFP
標準包裝: 450
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,LCD,LED,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
其它名稱: 935278626557
P89LPC9401_1
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
2 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment
× 4 LCD driver
s Serial ash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
s In-Application Programming (IAP) of the ash code memory. This allows changing the
code in a running application.
s Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
s Low voltage detect (brownout) allows a graceful system shutdown when power fails.
May optionally be congured as an interrupt.
s Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 9
A typical (total power-down with voltage comparators disabled).
s Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available.
s Congurable on-chip oscillator with frequency range options selected by user
programmed ash conguration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
s Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
s Programmable port output conguration options: quasi-bidirectional, open drain,
push-pull, input-only.
s Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
s LED drive capability (20 mA) on all port pins. A maximum limit is specied for the
entire chip.
s Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
s Only power and ground connections are required to operate the P89LPC9401 when
internal reset option is selected.
s Four interrupt priority levels.
s Eight keypad interrupt inputs, plus two additional external interrupt inputs.
s Schmitt trigger port inputs.
s Second data pointer.
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