參數(shù)資料
型號: P89LPC9401FBD,557
廠商: NXP Semiconductors
文件頁數(shù): 59/59頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 64-LQFP
標(biāo)準(zhǔn)包裝: 450
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LCD,LED,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
其它名稱: 935278626557
P89LPC9401_1
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
9 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment
× 4 LCD driver
P1.5/RST
11
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
When using an oscillator frequency above 12 MHz, the reset input function of
P1.5 must be enabled. An external circuit is required to hold the device in reset at
power-up until VDD has reached its specied level. When system power is
removed VDD will fall below the minimum specied operating voltage. When
using an oscillator frequency above 12 MHz, in some applications, an external
brownout detect circuit may be required to hold the device in reset when VDD falls
below the minimum specied operating range.
P1.6
10
I/O
P1.6 — Port 1 bit 6.
P1.7
9
I/O
P1.7 — Port 1 bit 7.
P2.0 to P2.3,
P2.5
I/O
Port 2: Port 2 is an 5-bit I/O port with a user-congurable output type. During reset
Port 2 latches are congured in the input only mode with the internal pull-up disabled.
The operation of Port 2 pins as inputs and outputs depends upon the port conguration
selected. Each port pin is congured independently. Refer to Section 7.13.1 “Port
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0
6
I/O
P2.0 — Port 2 bit 0.
P2.1
7
I/O
P2.1 — Port 2 bit 1.
P2.2/MOSI
18
I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When congured as master, this pin is output; when
congured as slave, this pin is input.
P2.3/MISO
19
I/O
P2.3 — Port 2 bit 3.
I/O
MISO — When congured as master, this pin is input, when congured as slave, this
pin is output.
P2.5/SPICLK
20
I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — SPI clock. When congured as master, this pin is output; when congured
as slave, this pin is input.
P3.0 to P3.1
I/O
Port 3: Port 3 is a 2-bit I/O port with a user-congurable output type. During reset
Port 3 latches are congured in the input only mode with the internal pull-up disabled.
The operation of Port 3 pins as inputs and outputs depends upon the port conguration
selected. Each port pin is congured independently. Refer to Section 7.13.1 “Port
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT
14
I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplier (when a crystal oscillator option is
selected via the ash conguration.
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source for
the RTC/system timer.
Table 3:
Pin description …continued
Symbol
Pin
Type Description
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