參數(shù)資料
型號(hào): P89LPC972FDH,129
廠商: NXP Semiconductors
文件頁數(shù): 3/66頁
文件大?。?/td> 0K
描述: MCU 80C51 8KB FLASH 20TSSOP
標(biāo)準(zhǔn)包裝: 75
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 568-8748-5
P89LPC972FDH,129-ND
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Table 4.
Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
Bit address
E7
E6
E5
E4
E3
E2
E1
E0
ACC*
Accumulator
E0H
00
0000 000
0
AUXR1
Auxiliary
function register
A2H
CLKLP
EBRR
ENT1
ENT0
SRST
0
-
DPS
00
0000 00x0
Bit address
F7
F6
F5
F4
F3
F2
F1
F0
B*
B register
F0H
00
0000 000
0
BRGR0[1] Baud rate
generator 0 rate
low
BEH
00
0000 000
0
BRGR1[1] Baud rate
generator 0 rate
high
BFH
00
0000 000
0
BRGCO
N
Baud rate
generator 0
control
BDH
-
SBRGS
BRGEN
00[1]
xxxx xx00
CMP1
Comparator 1
control register
ACH
-
CE1
CP1
CN1
OE1
CO1
CMF1
00[2]
xx00 0000
CMP2
Comparator 2
control register
ADH
-
CE2
CP2
CN2
OE2
CO2
CMF2
00[2]
xx00 0000
DIVM
CPU clock
divide-by-M
control
95H
00
0000 000
0
DPTR
Data pointer
(2 bytes)
DPH
Data pointer
high
83H
00
0000 000
0
DPL
Data pointer low
82H
00
0000 000
0
FMADRH Program flash
address high
E7H
00
0000 000
0
FMADRL Program flash
address low
E6H
00
0000 000
0
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