參數(shù)資料
型號: P89LPC972FDH,129
廠商: NXP Semiconductors
文件頁數(shù): 47/66頁
文件大?。?/td> 0K
描述: MCU 80C51 8KB FLASH 20TSSOP
標準包裝: 75
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 568-8748-5
P89LPC972FDH,129-ND
P89LPC97X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 8 June 2010
51 of 66
NXP Semiconductors
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
10. Dynamic characteristics
Table 12.
Dynamic characteristics (12 MHz)
VDD = 2.4 V to 5.5 V unless otherwise specified.
Tamb = 40 °Cto+85 °C for industrial applications, unless otherwise specified.[1][2]
Symbol
Parameter
Conditions
Variable clock
fosc =12MHz
Unit
Min
Max
Min
Max
fosc(RC)
internal RC oscillator
frequency
nominal f = 7.3728 MHz
trimmed to
±1% at
Tamb =25 °C; clock
doubler option = OFF
(default)
7.189
7.557
7.189
7.557
MHz
nominal f = 14.7456 MHz;
clock doubler option = ON,
VDD = 2.7 V to 5.5 V
14.378
15.114
14.378 15.114 MHz
fosc(WD)
internal watchdog
oscillator frequency
360
440
360
440
kHz
fosc
oscillator frequency
0
12
-
MHz
Tcy(clk)
clock cycle time
83
-
ns
fCLKLP
low-power select clock
frequency
08
-
MHz
Glitch filter
tgr
glitch rejection time
P1.5/RST pin
-
50
-
50
ns
any pin except P1.5/RST
-
15
-
15
ns
tsa
signal acceptance time
P1.5/RST pin
125
-
125
-
ns
any pin except P1.5/RST
50
-
50
-
ns
External clock
tCHCX
clock HIGH time
33
Tcy(clk) tCLCX
33
-
ns
tCLCX
clock LOW time
33
Tcy(clk) tCHCX
33
-
ns
tCLCH
clock rise time
-8
-
8
ns
tCHCL
clock fall time
-8
-
8
ns
Shift register (UART mode 0)
TXLXL
serial port clock cycle
time
16Tcy(clk)
-
1333
-
ns
tQVXH
output data set-up to
clock rising edge time
13Tcy(clk)
-
1083
-
ns
tXHQX
output data hold after
clock rising edge time
-Tcy(clk) + 20
-
103
ns
tXHDX
input data hold after
clock rising edge time
-0
-
0
ns
tXHDV
input data valid to clock
rising edge time
150
-
150
-
ns
SPI interface
fSPI
SPI operating frequency
slave
0
CCLK6
02.0
MHz
master
-
CCLK4
-3.0
MHz
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