參數(shù)資料
型號(hào): P89LPC980FDH,529
廠商: NXP Semiconductors
文件頁數(shù): 31/85頁
文件大?。?/td> 0K
描述: MCU 80C51 4KB FLASH 28TSSOP
標(biāo)準(zhǔn)包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 568-8750-5
P89LPC980FDH,529-ND
P89LPC980_982_983_985
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 15 June 2010
37 of 85
NXP Semiconductors
P89LPC980/982/983/985
8-bit microcontroller with accelerated two-clock 80C51 core
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
7.15.1 External interrupt inputs
The P89LPC980/982/983/985 has two external interrupt inputs as well as the Keypad
Interrupt function. The two interrupt inputs are identical to those present on the standard
80C51 microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC980/982/983/985 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume
operation. Refer to Section 7.17.3 “Power reduction modes” for details.
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