參數(shù)資料
型號(hào): P89LPC980FDH,529
廠商: NXP Semiconductors
文件頁數(shù): 68/85頁
文件大?。?/td> 0K
描述: MCU 80C51 4KB FLASH 28TSSOP
標(biāo)準(zhǔn)包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 568-8750-5
P89LPC980FDH,529-ND
P89LPC980_982_983_985
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 15 June 2010
70 of 85
NXP Semiconductors
P89LPC980/982/983/985
8-bit microcontroller with accelerated two-clock 80C51 core
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
TSPICYC
SPI cycle time
slave
6CCLK
-500
-
ns
master
4CCLK
-333
-
ns
tSPILEAD
SPI enable lead time
slave
250
-
250
-
ns
tSPILAG
SPI enable lag time
slave
250
-
250
-
ns
tSPICLKH
SPICLK HIGH time
master
2CCLK
-165
-
ns
slave
3CCLK
-250
-
ns
tSPICLKL
SPICLK LOW time
master
2CCLK
-165
-
ns
slave
3CCLK
-250
-
ns
tSPIDSU
SPI data set-up time
100
-
100
-
ns
master or slave
tSPIDH
SPI data hold time
100
-
100
-
ns
master or slave
tSPIA
SPI access time
slave
0
120
0
120
ns
tSPIDIS
SPI disable time
slave
0
240
-
240
ns
tSPIDV
SPI enable to output
data valid time
slave
-
240
-
240
ns
master
-
167
-
167
ns
tSPIOH
SPI output data hold
time
0-
0
-
ns
tSPIR
SPI rise time
SPI outputs (SPICLK,
MOSI, MISO)
-
100
-
100
ns
SPI inputs (SPICLK,
MOSI, MISO, SS)
-
2000
-
2000
ns
tSPIF
SPI fall time
SPI outputs (SPICLK,
MOSI, MISO)
-
100
-
100
ns
SPI inputs (SPICLK,
MOSI, MISO, SS)
-
2000
-
2000
ns
Table 14.
Dynamic characteristics (12 MHz) …continued
VDD = 2.4 V to 5.5 V unless otherwise specified.
Tamb = 40 °Cto+85 °C for industrial applications, unless otherwise specified.[1][2]
Symbol
Parameter
Conditions
Variable clock
fosc =12MHz
Unit
Min
Max
Min
Max
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