參數(shù)資料
型號: P89LPC985FDH,529
廠商: NXP Semiconductors
文件頁數(shù): 22/85頁
文件大?。?/td> 0K
描述: IC 80C51 MCU KB FLASH 28TSSOP
標準包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
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P8
9LPC
980_9
82_9
83_9
85
NXP
B.V
.
2010.
Al
lr
ig
h
ts
re
s
e
rv
ed.
Produ
ct
d
a
ta
sheet
Rev
.4
15
J
une
2010
29
o
f85
N
X
P
Semi
conductor
s
P89LPC980/982/983/985
8-
bit
microc
ont
roller
with
a
cce
lerat
e
d
tw
o-
cloc
k
80C5
1
core
[1]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[2]
All ports are in input only (high-impedance) state after power-up.
[3]
The RSTSRC register reflects the cause of the P89LPC980/982/983/985 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF;
the power-on reset value is x011 0000.
[4]
The only reset sources that affect these SFRs are power-on reset and watchdog reset.
[5]
On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
TH3
Timer/Counter 3
High Byte
EEH
00
0000 0000
TL3
Timer/Counter 3
Low Byte
EDH
00
0000 0000
T4CON
Timer/Counter 2
Control
CDH
PSEL4
ENT4
TIEN4
PWM4
EXEN4
TR4
C/NT4
CP/NRL4 00
0000 0000
TH4
Timer/Counter 4
High Byte
CCH
00
0000 0000
TL4
Timer/Counter 4
Low Byte
CBH
00
0000 0000
TINTF
Timer/Counters
2/3/4 Overflow
and External
Flags
CEH
-
TF4
EXF4
TF3
EXF3
TF2
EXF2
00
0000 0000
TRIM
Internal
oscillator trim
register
96H
RCCLK
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog
control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1
Watchdog
feed 1
C2H
WFEED2
Watchdog
feed 2
C3H
Table 6.
Special function registers - P89LPC983/985 …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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