參數(shù)資料
型號(hào)： P89LPC985FDH,529
廠(chǎng)商： NXP Semiconductors
文件頁(yè)數(shù)： 49/85頁(yè)
文件大?。?/td> 0K
描述： IC 80C51 MCU KB FLASH 28TSSOP
標(biāo)準(zhǔn)包裝： 51
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
包裝： 管件
P89LPC980_982_983_985
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 15 June 2010
53 of 85
NXP Semiconductors
P89LPC980/982/983/985
8-bit microcontroller with accelerated two-clock 80C51 core
7.25.1 Selectable internal reference voltage
An internal reference voltage generator may be used to supply a default reference when a
single comparator input pin is used. The user may program one of eight different values
for the internal reference voltage using the Comparator Reference register (CMPREF).
Each of the two comparators may use a different reference voltage.
7.25.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is
set whenever the comparator output changes state. The flag may be polled by software or
may be used to generate an interrupt. The two comparators use one common interrupt
vector. If both comparators enable interrupts, after entering the interrupt service routine,
the user needs to read the flags to determine which comparator caused the interrupt.
7.25.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down mode.
If a comparator interrupt is enabled (except in Total Power-down mode), a change of the
comparator output state will generate an interrupt and wake-up the processor. If the
comparator output to a pin is enabled, the pin should be configured in the push-pull mode
in order to obtain fast switching times while in Power-down mode. The reason is that with
the oscillator stopped, the temporary strong pull-up that normally occurs during switching
on a quasi-bidirectional port pin does not take place.
Comparators consume power in Power-down and Idle modes, as well as in the normal
operating mode. This fact should be taken into account when system power consumption
is an issue. To minimize power consumption, the user can disable the comparators via
PCONA.5, or put the device in Total Power-down mode.
(1) See Section 7.25.1 for more details.
Fig 18. Comparator input and output connections
comparator 1
CP1
CN1
(P0.4) CIN1A
(P0.3) CIN1B
(P0.5) CMPREF
Vref(cmp)(1)
OE1
change detect
CO1
CMF1
interrupt
002aac346
CMP1 (P0.6)
EC
change detect
CMF2
comparator 2
OE2
CO2
CMP2 (P0.0)
CP2
CN2
(P0.2) CIN2A
(P0.1) CIN2B
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