參數(shù)資料
型號(hào): P89V660FBC,557
廠商: NXP Semiconductors
文件頁(yè)數(shù): 75/90頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 706 (CN2011-ZH PDF)
配用: 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱(chēng): 568-2433
935280829557
P89V660FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
77 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
Table 72.
External clock drive
Symbol
Parameter
Oscillator
Unit
40 MHz
Variable
Min
Max
Min
Max
fosc
oscillator frequency
-
0
40
MHz
Tcy(clk)
clock cycle time
25
-
ns
tCHCX
clock HIGH time
8.75
-
0.35Tcy(clk)
0.65Tcy(clk)
ns
tCLCX
clock LOW time
8.75
-
0.35Tcy(clk)
0.65Tcy(clk)
ns
tCLCH
clock rise time
-
10
-
ns
tCHCL
clock fall time
-
10
-
ns
Fig 39. External clock drive waveform
tCHCL
tCLCX
tCHCX
Tcy(clk)
tCLCH
002aaa907
Table 73.
Serial port timing
Symbol
Parameter
Oscillator
Unit
40 MHz
Variable
Min
Max
Min
Max
TXLXL
serial port clock cycle time
0.3
-
12Tcy(clk)
-
s
tQVXH
output data set-up to clock rising
edge time
117
-
10Tcy(clk) 133 -
ns
tXHQX
output data hold after clock rising
edge time
0-
2Tcy(clk) 50
-
ns
tXHDX
input data hold after clock rising edge
time
0-
0
-
ns
tXHDV
input data valid to clock rising edge
time
-
117
-
10Tcy(clk) 133 ns
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