參數(shù)資料
型號(hào)： P90CE201
廠商： NXP Semiconductors N.V.
英文描述： 16-bit microcontroller
中文描述： 16位微控制器
文件頁(yè)數(shù)： 58/77頁(yè)
文件大小： 235K
代理商： P90CE201
August 1993
58
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
13.3
Timer registers
13.3.1
T
IMER
C
ONTROL
R
EGISTER
(TnCON)
The Timer Control Register (TnCON) controls the selection of the timer operating modes and the UART clock source.
Table 48
Description of TnCON bits.
SYMBOL
BIT
FUNCTION
TFn
TnCON.7
Timer n overflow flag. Set by a Timer n overflow and must be cleared by software.
TFn will not be set when either RCLKn = 1 or TCLKn = 1.
Timer n external flag. Set when either a capture or reload is caused by a negative
transition on external input Tn and when EXENn = 1. EXFn must be cleared by
software.
Receive Clock flag. When set, causes the UART to use Timer n overflow pulses
for its receive clock in Modes 1 and 3. See Table 50.
Transmit Clock flag. When set, causes the UART to use Timer n overflow pulses
for its transmit clock in Modes 1 and 3. See Table 50.
Timer n external enable flag. When set, allows a capture or reload to occur as a
result of a negative transition on external input Tn, if Timer n is not being used to
clock the UART. EXENn = 0 causes Timer 2 to ignore events at external input Tn.
Start/Stop control. TRn = 1 starts Timer n; TRn = 0 stops the timer.
Timer or Counter select. C/Tn = 0 selects the internal timer. C/Tn = 1 selects the
external event counter (edge triggered).
Capture/Reload flag. When set, captures will occur on valid transitions at external
input Tn, if EXEn2 = 1. When cleared, auto-reloads will occur upon either Timer n
overflows or valid transitions at Tn, if EXENn = 1. When either RCLKn = 1 or
TCLKn = 1, this bit is ignored and the timer is forced to auto-reload on a Timer n
overflow.
EXFn
TnCON.6
RCLKn
TnCON.5
TCLKn
TnCON.4
EXENn
TnCON.3
TRn
C/Tn
TnCON.2
TnCON.1
CP/RLn
TnCON.0
Fig.43 Timer Control Registers (TnCON).
bit 7
TFn
bit 6
EXFn
bit 5
RCLKn
bit 4
TCLKn
bit 3
EXENn
bit 2
TRn
bit 1
C/Tn
bit 0
CP/RLn
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