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| 型號： | P90CE201AEB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit microcontroller |
| 中文描述： | 16-BIT, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 41/77頁 |
| 文件大小： | 235K |
| 代理商： | P90CE201AEB |
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August 1993
41
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
8.2
I
2
C-bus interface registers
In the following register descriptions “n” represents the I
2
C-bus serial interface number (1 or 2); its associated registers
are identified using the same number.
8.2.1
S
ERIAL
C
ONTROL
R
EGISTER
(SnCON)
S1CON is located at address 8000 2007H; S2CON is located at address 8000 2017H. These registers have a default
value of 00H.
Table 30
Description of SnCON bits.
SYMBOL
BIT
FUNCTION
CR2
CR1
CR0
SnCON.7
SnCON.1
SnCON.0
Clock Rate. These three bits along with bit SYSCON2.12 (or SYSCON2.11) determine
the serial clock frequency that is generated in the master mode of operation. The
frequencies of 100 kHz and 400 kHz can be selected for the oscillators frequencies of
12, 16, 20 and 24 MHz, as shown in Table 31.
Enable Serial I/O. When ENS = 0; the serial interface I/O is disabled and reset. When
ENS = 1; the serial interface is enabled.
Start flag. When this bit is set in slave mode, the hardware checks the I
2
C-bus and
generates a START condition if the bus is free or after the bus becomes free. If the
device operates in Master Mode it will generate a repeated START condition.
Stop flag. If this bit is set in the master mode a STOP condition is generated. A STOP
condition detected on the I
2
C-bus clears this bit. The STOP bit may also be set in Slave
Mode in order to recover from an error condition. In this case no STOP condition is
generated to the I
2
C-bus, but the hardware releases the SDA and SCL lines and
switches to the not selected slave receiver mode. The STOP flag is cleared by the
hardware.
Serial Interrupt flag. This flag is set, and an interrupt is generated, after any of the
following events occur:
-
A START condition is generated in Master Mode
-
The own slave address has been received during AA = 1
-
The general call address has been received while SnADR.0 = 1 and AA = 1
-
A data byte has been received or transmitted in master mode
-
A data byte has been received or transmitted as selected slave
-
A STOP or START condition is received as selected slave receiver or transmitter.
While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must
be reset by software.
ENS
SnCON.6
STA
SnCON.5
STO
SnCON.4
SI
SnCON.3
Fig.25 Serial Control Register (SnCON)
bit 7
CR2
bit 6
ENS
bit 5
STA
bit 4
STO
bit 3
SI
bit 2
AA
bit 1
CR1
bit 0
CR0
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