August 1993
54
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
12 WATCHDOG TIMER
The P90CE201 contains a Watchdog Timer. Its purpose is
to reset the microcontroller, after a programmable time
interval, in the event of the microcontroller entering an
erroneous processor state. Erroneous processor states
can be caused by noise or RFI.
The Watchdog Timer consists of a 14-bit prescaler and an
8-bit timer (WDTIM). The prescaler is incremented by the
basic peripheral clock. WDTIM is incremented every
16384 cycles of the basic peripheral clock. It is the value
written to WDTIM that determines the Watchdog Timer
interval. If the timer interval is exceeded, the Watchdog
Timer overflows and the microcontroller is reset. In order
to prevent a timer overflow, the user program must reload
the Watchdog Timer within a time period shorter than the
programmed Watchdog Timer interval.
The Watchdog Timer is controlled by the Watchdog
Control Register (WDCON). WDCON can be read and
written to by software. After RESET, the Watchdog Timer
is disabled and WDCON contains A5H which clears both
the prescaler and WDTIM. The Watchdog Timer is
enabled by the first write operation to WDCON after
RESET. A running Watchdog Timer can only be disabled
by resetting the device.
WDTIM can be read on the fly but can only be written to if
WDCON has been loaded with 5AH. A successful write
operation to WDTIM also clears the prescaler and sets
WDCON to 00H in order to prevent further, unintentional,
write operations to WDTIM.
The Watchdog Timer interval (t) may be calculated as
WDTIM value
–
(
follows:
For example, if the basic peripheral clock frequency is 4
MHz, the Watchdog Timer interval will be within the range
4.1 ms to 1 second.
t
)
×
basic peripheral clock fre16384
=
Fig.39 Watchdog Timer.
handbook, full pagewidth
MLB253
INTERNAL BUS
write
WDTIM
PRESCALER
(14-BIT)
WDTIM
(8-BIT)
LOAD
CLEAREN
LOADEN
CLEAR
WDCON
INTERNAL BUS
CLEAR
BPCLK
to reset circuitry
from reset circuitry