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參數(shù)資料
| 型號： | PALCE20V8Q-25PI/4 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | EE CMOS 24-Pin Universal Programmable Array Logic |
| 中文描述： | EE PLD, 25 ns, PDIP24 |
| 封裝： | 0.300 INCH, SKINNY, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 479K |
| 代理商： | PALCE20V8Q-25PI/4 |
2
PALCE20V8 Family
USE
GAL
DEVICES
FOR
NEW
DESIGNS
The xed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output conguration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight independently congurable macrocells
(MC0-MC7). Each macrocell can be congured as a registered output, combinatorial output,
combinatorial I/O, or dedicated input. The programming matrix implements a programmable
AND logic array, which drives a xed OR logic array. Buffers for device inputs have
complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve
either as array inputs or as clock (CLK) and output enable (OE) for all ip-ops.
Unused input pins should be tied directly to VCC or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are automatically congured from the user’s
design specication, which can be in a number of formats. The design specication is processed
Programmable AND Array
40 x 64
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
OE
/I11
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
10
I1 – I10
CLK/I0
16491E
Input
Mux.
I13
MACRO
Input
Mux.
I12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PALCE20V8H-15PC/4 | KPTC 4C 4#20 SKT PLUG |
| PALCE20V8Q-15PC/4 | KPT 19C 19#20 PIN PLUG |
| PALCE20V8H-5JC/5 | EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-20JI/4 | EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE22V10H-10JC/5 | 24-Pin EE CMOS (Zero Power) Versatile PAL Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PALCE20V8Q-25PI5 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-5JC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-5JC4 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-5JC5 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-5JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
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