參數(shù)資料
型號(hào): PALCE20V8Q-25PI/4
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: EE CMOS 24-Pin Universal Programmable Array Logic
中文描述: EE PLD, 25 ns, PDIP24
封裝: 0.300 INCH, SKINNY, PLASTIC, DIP-24
文件頁數(shù): 8/25頁
文件大小: 479K
代理商: PALCE20V8Q-25PI/4
16
PALCE20V8 Family
USE
GAL
DEVICES
FOR
NEW
DESIGNS
SWITCHING WAVEFORMS
Notes:
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns to 5 ns typical.
tPD
Input or
Feedback
Combinatorial
Output
VT
a. Combinatorial output
16491E-5
tWH
Clock
c. Clock width
VT
tWL
16491E-7
VT
Input or
Feedback
Registered
Output
b. Registered output
tS
tCO
VT
tH
VT
Clock
16491E-6
VT
Input
Output
d. Input to output disable/enable
tER
tEA
VOH – 0.5V
VOL + 0.5V
16491E-8
VT
VT
OE
Output
e. OE to output disable/enable
tPZX
tPXZ
VOH – 0.5V
VOL + 0.5V
16491E-9
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