參數(shù)資料
型號: PALCE22V10H-20PI/4
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: 24-Pin EE CMOS (Zero Power) Versatile PAL Device
中文描述: EE PLD, 20 ns, PDIP24
封裝: 0.300 INCH, SKINNY, PLASTIC, DIP-24
文件頁數(shù): 22/34頁
文件大小: 691K
代理商: PALCE22V10H-20PI/4
PALCE22V10 and PALCE22V10Z Families
29
ROBUSTNESS FEATURES
The PALCE22V10X-X/5 devices have some unique features that make them extremely robust,
especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O
pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative
overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special
noise lter makes the programming circuitry completely insensitive to any positive overshoot that
has a pulse width of less than about 100 ns for the /5 version.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /5 VERSION DEVICES
Typical Input
Typical Output
Preload
Circuitry
ESD
Protection
and
Clamping
Feedback
Input
> 50 k
VCC
Programming
Voltage
Detection
Positive
Overshoot
Filter
Programming
Circuitry
Provides ESD
Protection and
Clamping
Programming
Pins only
16564-16
VCC
> 50 k
VCC
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相關代理商/技術參數(shù)
參數(shù)描述
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