參數(shù)資料
型號: PALCE22V10H-5JC/5
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: 24-Pin EE CMOS (Zero Power) Versatile PAL Device
中文描述: EE PLD, 5 ns, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 23/34頁
文件大?。?/td> 691K
代理商: PALCE22V10H-5JC/5
PALCE22V10 and PALCE22V10Z Families
3
Variable Input/Output Pin Ratio
The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.
Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Unused input pins should be tied to VCC or GND.
Registered Output Conguration
Each macrocell of the PALCE22V10 includes a D-type ip-op for data storage and
synchronization. The ip-op is loaded on the LOW-to-HIGH transition of the clock input. In the
registered conguration (S1 = 0), the array feedback is from Q of the ip-op.
Combinatorial I/O Conguration
Any macrocell can be congured as combinatorial by selecting the multiplexer path that bypasses
the ip-op (S1 = 1). In the combinatorial conguration, the feedback is from the pin.
0 = Programmed EE bit
1 = Erased (charged) EE bit
Figure 1. Output Logic Macrocell Diagram
16564E-004
CLK
S1
10
11
00
01
AR
SP
0
1
I/On
S0
D Q
Q
S1
S0
Output Conguration
0
Registered/Active Low
0
1
Registered/Active High
1
0
Combinatorial/Active Low
1
Combinatorial/Active High
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