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參數(shù)資料
| 型號： | PALCE610H-25JC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | USE GAL DEVICES FOR NEW DESIGNS |
| 中文描述： | EE PLD, 25 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 136K |
| 代理商： | PALCE610H-25JC |
2-386
PALCE610 Family
Power-Up Reset
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
This feature is valuable in simplifying state machine in-
itialization. A timing diagram and parameter table are
shown below. Due to the synchronous operation of the
power-up reset and wide range of ways VCC can rise to
its steady state, two conditions are required to insure a
valid power-up reset. These conditions are:
s The VCC rise must be monotonic.
s Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and feed-
back setup times are met.
Parameter
Symbol
Parameter Description
Max
Unit
tPR
Power-up Reset Time
1000
ns
tS
Input or Feedback Setup Time
tWL
Clock Width LOW
See Switching
Characteristics
12950G-15
tPR
tWL
tS
4 V
VCC
Power
Registered
Output
Clock
Power-Up Reset Waveform
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