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參數(shù)資料
| 型號(hào)： | PALCE610H-25PC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLD |
| 英文描述： | USE GAL DEVICES FOR NEW DESIGNS |
| 中文描述： | EE PLD, 25 ns, PDIP24 |
| 封裝： | 0.300 INCH, SKINNY, PLASTIC, DIP-24 |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 136K |
| 代理商： | PALCE610H-25PC |
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PALCE610 Family
FUNCTIONAL DESCRIPTION
The PALCE610 is a general purpose programmable
logic device. It has 16 independently-configurable ma-
crocells. Each macrocell can be configured as either
combinatorial or registered. The registers can be D, T,
J-K, or S-R type flip-flops. The device has 4 dedicated
input pins and 2 clock pins. Each clock pin controls 8 of
the 16 macrocells.
The programming matrix implements a programmable
AND logic array which drives a fixed OR logic array.
Buffers for device inputs have complementary outputs
to provide user-programmable input polarity. Unused in-
put pins should be tied to VCC or ground.
The array uses our electrically erasable technology.
An unprogrammed bit is disconnected and a pro-
grammed bit is connected. Product terms with all bits
unprogrammed assume the logical-HIGH state and
product terms with both the TRUE and Complement bits
programmed assume the logical-LOW state.
The programmable functions in the PALCE610 are
automatically configured from the user’s design specifi-
cations, which can be in a number of formats. The de-
sign specification is processed by development
software to verify the design and create a programming
file. This file, once downloaded to the programmer, con-
figures the design according to the user’s desired
function.
Macrocell Configurations
The PALCE610 macrocell can be configured as either
combinatorial or registered. Both the combinatorial and
registered configurations have output polarity control.
The register can be configured as a D, T, J-K, or
S-R type flip-flop. Figure 1 shows the possible
configurations.
Each macrocell can select as its clock either the corre-
sponding clock pin or the CLK/OE product term. If the
clock pin is selected, the output enable is controlled by
the CLK/OE product term. If the CLK/OE product term is
selected, the output is always enabled.
Combinatorial I/O
All 8 product terms are available to the OR gate. The
output-enable function is performed by the CLK/OE
product term.
Registered Configurations
There are 4 flip-flop types available: D, T, J-K and S-R.
The registers can be configured as synchronous or
asynchronous. In the synchronous configuration, the
clock is controlled by the clock input pin. The output en-
able is controlled by the product term function. In the
asynchronous configuration, the clock input is con-
trolled by the product term. The output is always
enabled.
In The D and T configurations, feedback can be either
from Q or the output pin. This allows D and T configura-
tions to be either outputs or I/O. In the J-K and S-R con-
figurations, feedback is only from Q; therefore, J-K and
S-R configurations are strictly outputs.
D Flip-Flop
All 8 product terms are available to the OR gate. The D
input polarity is controlled by an exclusive-OR gate. For
the D flip-flop, the output level is the D-input level at the
rising edge of the clock.
DQn
Qn+1
00
0
01
0
10
1
11
1
T Flip-Flop
All 8 product terms are available to the OR gate. The
T input polarity is controlled by an exclusive-OR gate.
For the T register, the output level toggles when the T
input is HIGH and remains the same when the T input is
LOW.
TQn
Qn+1
00
0
01
1
10
1
11
0
J-K Flip-Flop
The 8 product terms are divided between the J and K in-
puts. N product terms go to the J input and 8-N product
terms go to the K input, where N can range from 0 to 8.
Both the J and K inputs to the flip-flop have polarity con-
trol via exclusive-OR gates. The J-K flip-flop operation
is shown below.
JK
Qn
Qn+1
00
0
00
1
01
0
01
1
0
10
0
1
10
1
0
1
11
1
0
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