參數(shù)資料
型號(hào)： PC7447VGH1200L
廠商： Atmel Corp.
英文描述： PowerPC 7457 RISC Microprocessor
中文描述： 7457的PowerPC RISC微處理器
文件頁數(shù)： 48/66頁
文件大?。?/td> 522K
代理商： PC7447VGH1200L
48
PC7457/47 [Preliminary]
5345B–HIREL–02/04
Notes:
1. OV
DD
supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]); GV
DD
supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3], and L3_CLK[0:1])
and the L3 control signals L3_CNTL[0:1]; and V
DD
supplies power to the processor core and the PLL (after filtering to
become AV
DD
). For actual recommended value of V
IN
or supply voltages, see Table 3 on page 12.
2. Unused address pins must be pulled down to GND.
3. These pins require weak pull-up resistors (for example, 4.7 k
) to maintain the control signals in the negated state after they
have been actively negated and released by the PC7457 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull up to OV
DD
or negation by HRESET (inverse of HRESET), to ensure
proper operation.
6. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V).
To program the L3 interface, connect L3VSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V). If used, pull-down
resistors should be less than 250
.
7. Internal pull up on die.
8. Ignored in 60x bus mode.
9. These signals must be pulled down to GND if unused or if the PC7457 is in 60x bus mode.
10. These input signals for factory use only and must be pulled down to GND for normal machine operation.
11. Power must be supplied to GV
DD
, even when the L3 interface is disabled or unused.
12. It is recommended that this test signal be tied to HRESET; however, other configurations will not adversely affect
performance.
13. These input signals are for factory use only and must be pulled up to OV
DD
for normal machine operation.
14. These signals are for factory use only and must be left unconnected for normal machine operation.
15. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
16. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
17. These pins are internally connected to V
DD
. They are intended to allow an external device to detect the core voltage level
present at the processor core. If unused, they must be connected directly to V
DD
or left unconnected.
Signal Name
Pin Number
Active
I/O
I/F Select
(1)
TEST[0:5]
(13)
B10, H6, H10, D8, F9, F8
–
Input
BVSEL
TEST[6]
(10)
A9
–
Input
BVSEL
TMS
(7)
K4
High
Input
BVSEL
TRST
(7)(16)
C1
Low
Input
BVSEL
TS
(3)
P5
Low
I/O
BVSEL
TSIZ[0:2]
L1,H3,D1
High
Output
BVSEL
TT[0:4]
F1, F4, K8, A5, E1
High
I/O
BVSEL
WT
(3)
L2
Low
Output
BVSEL
V
DD
J9, J11, J13, J15, K10, K12, K14, L9, L11, L13, L15, M10, M12,
M14, N9, N11, N13, N15, P10, P12, P14
–
–
N/A
VDD_SENSE[0:1]
(17)
G11, J8
–
–
N/A
Table 17.
Pinout Listing for the PC7457, 483 CBGA Package (Continued)
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