參數(shù)資料
型號(hào)： PC755BMZFU300LD
英文描述： MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC
中文描述： 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料
文件頁(yè)數(shù)： 4/48頁(yè)
文件大?。?/td> 276K
代理商： PC755BMZFU300LD
4/48
PC755B/745B
1.1. General parameters
The following list provides a summary of the general parameters of the PC755B:
Technology
0.22 m CMOS, six-layer metal
Die size
6.61 mm x 7.73 mm (51 mm
2
)
Transistor count
6.75 million
Logic design
Fully-staticPackages
PC745B:
Surface mount 255 plastic ball grid array (PBGA)
PC755B:
Surface mount 360 plastic ball grid array (PBGA)
Core power supply: 2.0V 100 mV dc (nominal; see table 5 for recommended operating conditions)
I/O power supply
1.8V 100 mV dc or
2.0V 100 mV dc or
3.3V 165mV dc (input thresholds are configuration pin selectable)
1.2. Features
This section summarizes features of the PC755B’s implementation of the PowerPC architecture. Major features of the PC755B are as
follows:
Branch processing unit
-
Four instructions fetched per clock
-
One branch processed per cycle (plus resolving 2 speculations)
-
Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
-
512-entry branch history table (BHT) for dynamic prediction
-
64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating branch delay slots
Dispatch unit
-
Full hardware detection of dependencies (resolved in the execution units)
-
Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-
point)
-
Serialization control (predispatch, postdispatch, execution serialization)
Decode
-
Register file access
-
Forwarding control
-
Partial instruction decode
Completion
-
6 entry completion buffer
-
Instruction tracking and peak completion of two instructions per cycle
-
Completion of instructions in program order while supporting out-of- order instruction execution, completion serialization and
all instruction flow changes
Fixed Point Units (FXUs) that share 32 GPRs for integer operands
-
Fixed Point Unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical
-
Fixed Point Unit 2 (FXU2)-shift, rotate, arithmetic, logical
-
Single-cycle arithmetic, shifts, rotates, logical
-
Multiply and divide support (multi-cycle)
-
Early out multiply
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