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參數(shù)資料
| 型號： | PC755BMZFU300LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料 |
| 文件頁數(shù)： | 5/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC755BMZFU300LD |
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PC755B/745B
5/48
Floating-point unit and a 32-entry FPR file
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Support for IEEE-754 standard single and double precision floating point arithmetic
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Hardware support for divide
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Hardware support for denormalized numbers
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Single-entry reservation station
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Supports non-IEEE mode for time-critical operations
System unit
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Executes CR logical instructions and miscellaneous system instructions
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Special register transfer instructions
Load/store unit
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One cycle load or store cache access (byte, half-word, word, double-word)
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Effective address generation
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Hits under misses (one outstanding miss)
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Single-cycle unaligned access within double word boundary
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Alignment, zero padding, sign extend for integer register file
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Floating point internal format conversion (alignment, normalization)
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Sequencing for load/store multiples and string operations
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Store gathering
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Cache and TLB instructions
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Big and Little-endian byte addressing supported
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Misaligned Little-endian supported
Level 1 Cache structure
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32K, 32-byte line, 8-way set associative instruction cache (iL1)
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32K, 32-byte line, 8-way set associative data cache (dL1)
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Cache locking for both instruction and data caches, selectable by group of ways
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Single-cycle cache access
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Pseudo least-recently used (PLRU) replacement
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Copy-back or Write Through data cache (on a page per page basis)
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Supports all PowerPC memory coherency modes
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Non-Blocking instruction and data cache (one outstanding miss under hits)
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No snooping of instruction cache
Level 2 (L2) Cache Interface (not implemented on PC745B)
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Internal L2 cache controller and tags; external data SRAMs
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256K, 512K, and 1Mbyte 2-way set associative L2 cache support
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Copyback or write-through data cache (on a page basis, or for all L2)
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Instruction-only mode and data-only mode.
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64byte (256K/512K) or 128byte (1M) sectored line size
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Supports flow through (register-buffer) synchronous burst SRAMs, pipelined (register-register) synchronous burst SRAMs
(3-1-1-1 or strobeless 4-1-1-1) and pipelined (register-register) late-write synchronous burst SRAMs
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L2 configurable to direct mapped SRAM interface or split cache/direct mapped or private memory
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Core-to-L2 frequency divisors of 1, 1.5, 2, 2.5, and 3 supported
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64 bit data bus
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Selectable interface voltages of 1.8V/2.0V and 3.3V
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Parity checking on both L2 address and data
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC755BMZFU350LD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| PC755BMZFU400LD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| PC755BVGH300LE | 制造商:e2v technologies 功能描述:PC755BVGH300LE - Trays |
| PC755BVGH350LE | 制造商:e2v technologies 功能描述:POWERPC 755 32-BIT RISC MICROPROCESSOR - 350MHZ, 2.0V, HITCE, IND TEMP 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.22UM 350MHZ 2.5V/3.3V 360HITCE CBGA - Trays |
| PC755BVGU300LE | 制造商:e2v technologies 功能描述:PC755BVGU300LE - Trays |
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