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| 型號： | PC755BVZFU350LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料 |
| 文件頁數(shù)： | 33/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC755BVZFU350LD |
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PC755B/745B
33/48
4.2.5. IEEE 1149.1 AC Timing Specifications
4.2.5.1. Timing Specifications
Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 18, Figure 19, Figure 20, and Figure 21.
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK)1
At recommended operating conditions (See Table 5 )
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
fTCLK
0
33.3
MHz
TCK cycle time
tTCLK
30
—
ns
TCK clock pulse width measured at 1.4V
tJHJL
15
—
ns
TCK rise and fall times
tJR & tJF
0
2
ns
TRST assert time
tTRST
25
—
ns
2
Input Setup Times:
Boundary-scan data
TMS, TDI
tDVJH
t
IVJH
4
0
—
—
ns
3
Input Hold Times:
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
15
12
—
—
ns
3
Valid Times:
Boundary-scan data
TDO
tJLDV
t
JLOV
—
—
4
4
ns
4
Output Hold Times:
Boundary-scan data
TDO
tJLDH
tJLOH
20
12
—
—
ns
4
TCK to output high impedance:
Boundary-scan data
TDO
t
JLDZ
tJLOZ
3
3
19
9
ns
4,5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 ohm
load (See Figure 18 ). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the PC755B.
OUTPUT
OVdd/2
RL = 50
Z0 = 50
Figure 18 : ALTERNATE AC Test Load for the JTAG Interface
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