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參數(shù)資料
| 型號： | PC755CMGU400LE |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerPC 755/745 RISC Microprocessor |
| 中文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | CERAMIC, BGA-360 |
| 文件頁數(shù)： | 25/50頁 |
| 文件大?。?/td> | 1064K |
| 代理商： | PC755CMGU400LE |
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25
PC755/745
2138D–HIREL–06/03
Clock AC Specifications
Table 12 provides the clock AC timing specifications as defined in Table 3.
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0
-
3] settings must be chosen such that the resulting SYSCLK (bus) fre-
quency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0
-
3] signal description in Table 18,” for valid PLL_CFG[0
-
3] settings
2. Rise and fall times measurements are now specified in terms of slew rates, rather than time to account for selectable I/O bus
interface levels. The minimum slew rate of 1v/ns is equivalent to a 2ns maximum rise/fall time measured at 0.4V and 2.4V or
a rise/fall time of 1ns measured at 0.4V to 1.4V.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter – short term and long term combined and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL
-
relock time is the maximum amount of time required for
PLL lock after a stable V
DD
and SYSCLK are reached during the power
-
on reset sequence. This specification also applies
when the PLL has been disabled and subsequently re
-
enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL
-
relock time during the power
-
on reset sequence.
Figure 10 provides the SYSCLK input timing diagram.
Figure 10.
SYSCLK Input Timing Diagram
Table 12.
Clock AC Timing Specifications at Recommended Operating Conditions (See Table 5)
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
300 MHz
350 MHz
400 MHz
Min
Max
Min
Max
Min
Max
Processor frequency
(1)
f
core
200
300
200
350
200
400
MHz
VCO frequency
(1)
f
VCO
400
600
400
700
400
800
MHz
SYSCLK frequency
(1)
f
SYSCLK
25
100
25
100
25
100
MHz
SYSCLK cycle time
t
SYSCLK
10
40
10
40
10
40
ns
SYSCLK rise and fall time
(2)
t
KR
& t
KF
–
2
–
2
–
2
ns
t
KR
& t
KF
–
1.4
–
1.4
–
1.4
ns
SYSCLK duty cycle measured at OV
DD
/2
(3)
SYSCLK jitter
(3)(4)
t
KHKL
/t
SYSCLK
40
60
40
60
40
60
%
–
150
–
150
–
150
ps
Internal PLL relock time
(3)(5)
–
100
–
100
–
100
μs
SYSCLK
VM
VM
VM
KVIH
KVIL
VM = Midpoint Voltage (OVDD/2)
t
SYSCLK
t
KR
t
KF
t
KHKL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC755CMZFU300LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
| PC755CMZFU350LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
| PC755CMZFU366LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
| PC755CMZFU400LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
| PC755CVGH400LE | 制造商:e2v technologies 功能描述:POWERPC 755 32-BIT RISC MICROPROCESSOR - 400MHZ, 2.0V, HITCE, IND TEMP 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.22UM 400MHZ 2.5V/3.3V 360HITCE CBGA - Trays |
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