參數(shù)資料
型號： PC8245MTPU333D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Integrated Processor Family
中文描述： 32-BIT, 333 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.27 MM PITCH, TBGA-352
文件頁數(shù)： 53/61頁
文件大小： 429K
代理商： PC8245MTPU333D
53
PC8245
2171D–HIREL–06/04
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal
is optional in the IEEE 1149.1 specification, but is provided on all processors that imple-
ment the PowerPC architecture. While it is possible to force the TAP controller to the
reset state using only the TCK and TMS signals, more reliable power-on reset perfor-
mance will be obtained if the TRST signal is asserted during power-on reset. Because
the JTAG interface is also used for accessing the common on-chip processor (COP)
function, simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC
with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port
requires the ability to independently assert HRESET or TRST in order to fully control the
processor. If the target system has independent reset sources, such as voltage moni-
tors, watchdog timers, power supply failures, or push-button switches, then the COP
reset signals must be merged into these signals with logic.
The arrangement shown in Figure 30 on page 54 allows the COP to independently
assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If
the JTAG interface and COP header will not be used, TRST should be tied to HRESET
so that it is asserted when the system reset signal (HRESET) is asserted ensuring that
the JTAG scan chain is initialized during power-on.
The COP header shown in Figure 30 on page 54 adds many benefits
—
breakpoints,
watchpoints, register and memory examination/modification, and other standard debug-
ger features are possible through this interface
—
and can be as inexpensive as an
unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on
the 0.025" square-post, 0.100" centered header assembly (often called a Berg header).
There is no standardized way to number the COP header shown in Figure 30 on page
54; consequently, many different pin numbers have been observed from emulator ven-
dors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right
then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as
with an IC). Regardless of the numbering, the signal placement recommended in Figure
30 on page 54 is common to all known emulators.
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