參數(shù)資料
型號: PC9S08AC128CFGE
廠商: Freescale Semiconductor
文件頁數(shù): 24/40頁
文件大小: 0K
描述: MCU 8BIT 128K FLASH 44-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
30
Freescale Semiconductor
3.11
SPI Characteristics
Table 3-14 and Figure 3-15 through Figure 3-18 describe the timing requirements for the SPI system.
Table 3-14. SPI Electrical Characteristic
Num1
1 Refer to Figure 3-15 through Figure 3-18.
C
Characteristic2
2 All timing is shown with respect to 20% V
DD and 70% VDD, unless noted; 100 pF load on all SPI
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
Symbol
Min
Max
Unit
Operating frequency3
Master
Slave
3 Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
fop
fBus/2048
dc
fBus/2
fBus/4
Hz
1
Cycle time
Master
Slave
tSCK
2
4
2048
tcyc
2
Enable lead time
Master
Slave
tLead
1/2
tSCK
3
Enable lag time
Master
Slave
tLag
1/2
tSCK
4
Clock (SPSCK) high time
Master and Slave
tSCKH
1/2 tSCK – 25
ns
5
Clock (SPSCK) low time Master
and Slave
tSCKL
1/2 tSCK – 25
ns
6
Data setup time (inputs)
Master
Slave
tSI(M)
tSI(S)
30
ns
7
Data hold time (inputs)
Master
Slave
tHI(M)
tHI(S)
30
ns
8
Access time, slave4
4 Time to data active from high-impedance state.
tA
040
ns
9
Disable time, slave5
5 Hold time to high-impedance state.
tdis
—40
ns
10
Data setup time (outputs)
Master
Slave
tSO
25
ns
11
Data hold time (outputs)
Master
Slave
tHO
–10
ns
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