參數(shù)資料
型號(hào): PCA9504ADGG
廠商: NXP SEMICONDUCTORS
元件分類: 標(biāo)準(zhǔn)邏輯
英文描述: Glue chip 4
中文描述: SPECIALTY LOGIC CIRCUIT, PDSO56
封裝: PLASTIC, TSSOP-56
文件頁(yè)數(shù): 13/29頁(yè)
文件大?。?/td> 146K
代理商: PCA9504ADGG
Philips Semiconductors
Product data
PCA9504A
Glue chip 4
2004 May 11
13
AC CHARACTERISTICS
V
CC1
= 3.3 V; V
CC
= 5.0 V
LIMITS
SYMBOL
PARAMETER
T
amb
= 0 C to +70 C
UNITS
NOTES
MIN
TYP
MAX
t
RESET
t
RESET_FALL
RSMRST
4.0
100
ms
RSMRST
100
ns
t
PHL
/t
PLH
Propagation Delay
AUD_EN to AUD_RST
PCIRST to AUD_RST
PCIRST to IDE_RSTDRV
PCIRST to PCIRST_OUT
1.0
11.0
ns
t
PLH
/t
PHL
Propagation Delay
MUTE_AUD to MUTE_SHDN
2.5
6.0
ns
t
PLH
/t
PHL
Propagation Delay
PWRGD_PS to PWRGD_3V
FPRST to PWRGD_3V
4.5
11.0
ns
t
PLH
/t
PHL
Propagation Delay
HSYNC_3V to HSYNC_5V
VSYNC_3V to VSYNC_5V
2.0
5.0
ns
t
PLH
/t
PHL
Propagation Delay
PWRGD_PS to SCK_BJT_GATE
FPRST to SCK_BJT_GATE
1.0
6.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
PRIMARY_HD to HD_LED
PRIMARY_HD to HD_LED
PRIMARY_HD to HD_LED
1.0
5.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
GP1_INA to GP1_OUT
GP2_INA to GP1_OUT
3.0
25.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
GP2_IN to GP2_OUT
3.0
7.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
GP3_IN to GP3_OUT
1.0
4.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
SLP_S3 to BACKFEED_OUT
PRWGD_PS to BACKFEED_OUT
1.0
6.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
CPU_PRESENT to PS_ON
2.0
10.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
SLP_S3 to PS_ON
2.0
10.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
BACKFEED_OUT to
LATCHED_BACKFEED_OUT
2.0
11.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
SLP_S5 to YLW_LED
SLP_S5 to GRN_LED
YLW_BLNK to YLW_LED
GRN_BLNK to GRN_LED
1.0
5.0
ns
t
PLZ
/t
PZL
Open Drain Prop Delay
3V_DDOSDA to 5V_DDOSDA
3V_DDOSDA to 5V_DDOSDA
1.0
5.0
ns
t
r
, t
f
Rise and Fall Times
HSYNC_5V
VSYNC_5V
3.5
ns
t
r
, t
f
Rise and Fall Times
LATCHED_BACKFEED_OUT
1.0
μ
s
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