參數(shù)資料
型號: PCA9504ADGG
廠商: NXP SEMICONDUCTORS
元件分類: 標(biāo)準(zhǔn)邏輯
英文描述: Glue chip 4
中文描述: SPECIALTY LOGIC CIRCUIT, PDSO56
封裝: PLASTIC, TSSOP-56
文件頁數(shù): 8/29頁
文件大?。?/td> 146K
代理商: PCA9504ADGG
Philips Semiconductors
Product data
PCA9504A
Glue chip 4
2004 May 11
8
SYMBOL
UNIT
LIMITS
TEST CONDITION
PARAMETER
T
amb
= 0
°
C to +70
°
C
TYP
MAX
MIN
I
IH
SCSI
Input leakage HIGH
V
IH
= 5VSB
–1
1
μ
A
V
IH
V
IL
Hys
HIGH-level input voltage
0.7*5VSB
V
LOW-level input voltage
0.2*5VSB
V
Input hysteresis
400
mV
μ
A
μ
A
I
IL
I
IH
FPRST
Input leakage LOW
V
IL
= 0 V
V
IH
= 5VSB
–88
–26
Input leakage HIGH
–1
1
V
IH
V
IL
Hys
HIGH-level input voltage
0.7*5VSB
V
LOW-level input voltage
0.2*5VSB
V
Input hysteresis
400
mV
μ
A
μ
A
I
IL
I
IH
PWRGD_PS
Input leakage LOW
V
IL
= 0 V
V
IH
= 5VSB
–88
–26
Input leakage HIGH
–1
1
V
IH
V
IL
Hys
HIGH-level input voltage
0.7*5VSB
V
LOW-level input voltage
0.2*5VSB
V
Input hysteresis
400
mV
μ
A
μ
A
I
IL
I
IH
GPO_FLUSH_CACHE/GP2_IN
Input leakage LOW
V
IL
= 0 V
V
IH
= 5VSB
–88
–26
Input leakage HIGH
–1
1
V
IH
V
IL
I
L
I
IH
INIT / GP1_INA (GP Mode)
HIGH-level input voltage
2.2
V
LOW-level input voltage
0.8
V
μ
A
μ
A
Input leakage
V
IL
= 0 V
V
IH
= 5 V
–88
–26
Input leakage
–1
1
V
IH
HIGH-level input voltage
Part is strapped for GP
mode
2.4
V
V
IL
LOW-level input voltage
Part is strapped for GP
mode
0.8
V
I
L
Input leakage
Part is strapped for GP
mode
–1
1
μ
A
VCCP_V
ref
INIT / GP1_INA (Flush Mode)
Bias voltage
GP mode
1.95
2.1
V
V
IH
V
IL
I
IL
VCCP_V
ref
HIGH-level input voltage
FLUSH mode
1.5
V
LOW-level input voltage
FLUSH mode
0.4
V
μ
A
V
Input leakage
FLUSH mode
–1
1
Bias voltage
FLUSH mode
0.95
1.1
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