參數(shù)資料
型號: PCA9530DP
廠商: NXP Semiconductors N.V.
元件分類: LED驅(qū)動器
英文描述: 2-bit I2C-bus LED dimmer
封裝: PCA9530D<SOT96-1 (SO8)|<<http://www.nxp.com/packages/SOT96-1.html<1<week 5, 2005,;PCA9530D<SOT96-1 (SO8)|<<http://www.nxp.com/packages/SOT96-1.html<1<week 5, 2005,;
文件頁數(shù): 22/24頁
文件大小: 143K
代理商: PCA9530DP
PCA9530_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 February 2009
7 of 24
NXP Semiconductors
PCA9530
2-bit I2C-bus LED dimmer
6.6 External RESET
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9530 registers and I2C-bus state machine will be held in their default states until the
RESET input is once again HIGH.
This input requires a pull-up resistor to VDD if no active connection is used.
7.
Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 6).
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is dened as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is dened as the STOP
condition (P) (see Figure 7).
Fig 6.
Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 7.
Denition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
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