參數(shù)資料
型號: PCA9537
廠商: NXP Semiconductors N.V.
英文描述: 4-bit I2C and SMBus low power I/O port with interrupt and reset
中文描述: 4位I2C和SMBus低功率的I / O端口中斷和復位
文件頁數(shù): 11/17頁
文件大?。?/td> 163K
代理商: PCA9537
Philips Semiconductors
4-bit I
2
C and SMBus low power I/O port
with interrupt and reset
Product data sheet
PCA9537
2004 Nov 29
11
AC SPECIFICATIONS
SYMBOL
PARAMETER
STANDARD MODE
I
2
C-bus
MIN
0
FAST MODE
I
2
C-bus
MIN
0
UNITS
MAX
100
MAX
400
f
SCL
t
BUF
t
HD;STA
t
SU;STA
t
SU;STO
t
HD;DAT
t
VD;ACK
t
VD;DAT
t
SU;DAT
t
LOW
t
HIGH
t
F
t
R
t
SP
Operating frequency
kHz
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
Bus free time between STOP and START conditions
4.7
1.3
Hold time after (repeated) START condition
4.0
0.6
Repeated START condition setup time
4.7
0.6
Setup time for STOP condition
4.0
0.6
Data in hold time
Valid time for ACK condition
2
Data out valid time
3
0
0
0.3
3.45
0.1
0.9
300
50
Data setup time
250
100
ns
μ
s
μ
s
ns
Clock LOW period
4.7
1.3
Clock HIGH period
4.0
0.6
Clock/Data fall time
300
20 + 0.1 C
b1
20 + 0.1 C
b1
300
Clock/Data rise time
1000
300
ns
Pulse width of spikes that must be suppressed by the
input filters
50
50
ns
Port Timing
t
PV
t
PS
t
PH
Output data valid
200
200
ns
Input data setup time
100
100
ns
μ
s
Input data hold time
1
1
Interrupt Timing
t
IV
t
IR
Interrupt valid
4
4
μ
s
μ
s
Interrupt reset
4
4
RESET
t
W
t
REC
t
RESET
Reset pulse width
4
4
ns
Reset recovery time
0
0
ns
Time to reset
400
400
ns
NOTES:
1. C
b
= total capacitance of one bus line in pF.
2. t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
3. t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
t
SP
t
BUF
t
HD;STA
P
P
S
t
LOW
t
R
t
HD;DAT
t
F
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
SU00645
Figure 12. Definition of timing
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