參數(shù)資料
型號： PCA9544ARGWR
廠商： Texas Instruments, Inc.
英文描述： 4-CHANNEL IC AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC
中文描述： 4通道多路轉(zhuǎn)換集成電路和SMBus與中斷邏輯
文件頁數(shù)： 11/23頁
文件大?。?/td> 578K
代理商： PCA9544ARGWR
www.ti.com
I
2
C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see
Figure 12
)
Switching Characteristics
over recommended operating free-air temperature range, C
L
≤
100 pF (unless otherwise noted) (see
Figure 10
)
Interrupt Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146A–OCTOBER 2005–REVISED OCTOBER 2005
STANDARD-MODE
I
2
C BUS
MIN
0
4
4.7
FAST-MODE
I
2
C BUS
MIN
UNIT
MAX
100
MAX
400
f
scl
t
sch
t
scl
t
sp
t
sds
t
sdh
t
icr
t
icf
t
ocf
t
buf
t
sts
t
sth
t
sps
t
vdL(Data)
t
vdH(Data)
I
2
C clock frequency
I
2
C clock high time
I
2
C clock low time
I
2
C spike time
I
2
C serial-data setup time
I
2
C serial-data hold time
I
2
C input rise time
I
2
C input fall time
I
2
C output fall time (10-pF to 400-pF bus)
I
2
C bus free time between stop and start
I
2
C start or repeated start condition setup
I
2
C start or repeated start condition hold
I
2
C stop condition setup
Valid-data time (high to low)
(3)
Valid-data time (low to high)
(3)
0
kHz
μ
s
μ
s
ns
ns
μ
s
ns
ns
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
0.6
1.3
50
50
250
0
(1)
100
0
(1)
1000
300
300
20 + 0.1C
b(2)
20 + 0.1C
b(2)
20 + 0.1C
b(2)
300
300
300
4.7
4.7
1.3
0.6
0.6
0.6
4
4
SCL low to SDA output low valid
SCL low to SDA output high valid
ACK signal from SCL low
to SDA output low
1
1
0.6
0.6
t
vd(ack)
Valid-data time of ACK condition
1
1
μ
s
C
b
I
2
C bus capacitive load
400
400
pF
(1)
A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the V
IH
min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
C
= total bus capacitance of one bus line in pF
Data taken using a 1-k
pullup resistor and 50-pF load (see
Figure 10
).
(2)
(3)
FROM
(INPUT)
TO
PARAMETER
MIN
MAX
UNIT
(OUTPUT)
R
ON
= 20
, C
L
= 15 pF
R
ON
= 20
, C
L
= 50 pF
0.3
t
pd(1)
Propagation delay time
SDA or SCL
SDn or SCn
μ
s
1
4
2
t
iv
t
ir
Interrupt valid time
(2)
Interrupt reset delay time
(2)
INTn
INTn
INT
INT
μ
s
μ
s
(1)
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
Data taken using a 4.7-k
pullup resistor and 100-pF load (see
Figure 11
).
(2)
PARAMETER
MIN
MAX
UNIT
μ
s
μ
s
t
PWRL
t
PWRH
Low-level pulse duration rejection of INTn inputs
(1)
High-level pulse duration rejection of INTn inputs
(1)
1
0.5
(1)
Data taken using a 4.7-k
pullup resistor and 100-pF load (see
Figure 11
).
11
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