Table 4. DC ELECTRICAL CHARACTERISTICS VDD
參數(shù)資料
型號: PCA9655EDWR2G
廠商: ON Semiconductor
文件頁數(shù): 16/20頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 16B SOIC-24
標準包裝: 1
接口: I²C 總線,SM 總線
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時鐘: 100kHz
電源電壓: 1.65 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 24-SOIC
包裝: 標準包裝
其它名稱: PCA9655EDWR2GOSDKR
PCA9655E
http://onsemi.com
5
Table 4. DC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V, unless otherwise specified.
Symbol
Parameter
Conditions
TA = 555C to +1255C
Unit
Min
Typ
Max
SUPPLIES
ISTB
Standby Current
Standby mode; no load;
VI = 0 V; fSCL = 0 Hz; I/O = inputs
VI = VDD; fSCL = 0 Hz; I/O = inputs
1.1
0.25
1.5
1
mA
VPOR
PowerOn Reset Voltage
(Note 5)
1.5
1.65
V
INPUT SCL; Input / Output SDA
VIH
HighLevel Input Voltage
0.7 x VDD
V
VIL
LowLevel Input Voltage
0.3 x VDD
V
IOL
LowLevel Output Current
VOL = 0.4 V; VDD < 2.3 V
10
mA
VDD w 2.3 V
20
IL
Leakage Current
VI = VDD or 0 V
$1
mA
CI
Input Capacitance
VI = 0 V
4.6
6
pF
I/Os
VIH
HighLevel Input Voltage
0.7 x VDD
V
VIL
LowLevel Input Voltage
0.3 x VDD
V
IOL
LowLevel Output Current
(Note 6)
VOL = 0.5 V; VDD = 1.65 V
VOL = 0.5 V; VDD = 2.3 V
VOL = 0.5 V; VDD = 3.0 V
VOL = 0.5 V; VDD = 4.5 V
8
12
17
25
20
28
35
42
mA
IOL(tot)
Total LowLevel Output Current
(Note 6)
VOL = 0.5 V; VDD = 4.5 V
400
mA
VOH
HighLevel Output Voltage
IOH = 3 mA; VDD = 1.65 V
IOH = 4 mA; VDD = 1.65 V
IOH = 8 mA; VDD = 2.3 V
IOH = 10 mA; VDD = 2.3 V
IOH = 8 mA; VDD = 3.0 V
IOH = 10 mA; VDD = 3.0 V
IOH = 8 mA; VDD = 4.5 V
IOH = 10 mA; VDD = 4.5 V
1.2
1.1
1.8
1.7
2.6
2.5
4.1
4.0
V
ILH
Input Leakage Current
VDD = 5.5 V; VI = VDD
1
mA
ILL
Input Leakage Current
VDD = 5.5 V; VI = 0 V
100
mA
CI/O
Input / Output Capacitance
(Note 7)
5.0
6.0
pF
INTERRUPT (INT)
IOL
LowLevel Output Current
VOL = 0.4 V
6.0
mA
CO
Output Capacitance
5.0
5.5
pF
INPUTS AD0, AD1, AD2
VIH
HighLevel Input Voltage
0.7 x VDD
V
VIL
LowLevel Input Voltage
0.3 x VDD
V
IL
Leakage Current
VI = VDD or 0 V
$1
mA
CI
Input Capacitance
4.5
5.0
pF
5. The poweron reset circuit resets the I2C bus logic with VDD < VPOR and set all I/Os to logic 1 upon powerup. Thereafter, VDD must be lower
than 0.2 V to reset the part.
6. Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal bussing limits.
7. The value is not tested, but verified on sampling basis.
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