參數(shù)資料
型號(hào)： PCA9655EDWR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 16B SOIC-24
標(biāo)準(zhǔn)包裝： 1
接口： I²C 總線，SM 總線
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 100kHz
電源電壓： 1.65 V ~ 5.5 V
工作溫度： -55°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： PCA9655EDWR2GOSDKR
PCA9655E
http://onsemi.com
15
Figure 12. Bit Transfer
data line
stable;
data valid
change
of data
allowed
SDA
SCL
START and STOP Conditions
Both data and clock lines remain HIGH when the bus is
not busy. A START condition (S) occurs when there is a
HIGHtoLOWtransition of the data line while the clock is
HIGH. A STOP condition (P) occurs when there is a
LOWtoHIGHtransition of the data line while the clock is
HIGH (see Figure 13).
Figure 13. Definition of START and STOP Conditions
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
System Configuration
A device generating a message is a ‘transmitter’; a device
receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled
by the master are the ‘slaves’ (see Figure 14).
Figure 14. System Configuration
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2CBUS
MULTIPLEXER
SLAVE
Acknowledge
The number of data bytes transferred between the START
and the STOP conditions from transmitter to receiver is not
limited. Each 8bit byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter, whereas the master generates an extra clock
pulse for the acknowledge bit.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also, a master
must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The
device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, such that the SDA line
is stable LOW during the HIGH period of the acknowledge
clock pulse; setup time and hold time must be taken into
account.
A master receiver signals an end of data to the transmitter
by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event, the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
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