參數(shù)資料
型號(hào): PCA9672D,512
廠商: NXP Semiconductors
文件頁(yè)數(shù): 36/36頁(yè)
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 16SOIC
標(biāo)準(zhǔn)包裝: 48
接口: I²C
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 管件
包括: POR
其它名稱: 935282746512
PCA9672D
PCA9672D-ND
PCA9672
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 27 May 2013
9 of 36
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset
Simple code for reading Device ID:
<S> <F8h> <ACK> <slave address> <ACK> <Sr> <F9h > <ACK> <DATA1>
<ACK> <DATA2> <ACK> <DATA3> <NACK> <P>
8.
I/O programming
8.1 Quasi-bidirectional I/Os
A quasi-bidirectional I/O is an input or output port without using a direction control register.
Whenever the master reads the register, the value returned to master depends on the
actual voltage or status of the pin. At power-on, all the ports are HIGH with a weak 100
A
internal pull-up to VDD, but can be driven LOW by an internal transistor, or an external
signal. The I/O ports are entirely independent of each other, but each I/O octal is
controlled by the same read or write data byte.
Advantages of the quasi-bidirectional I/O over totem pole I/O include:
Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves
die size and therefore cost. LED drive only requires an internal transistor to ground,
while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O
have both n-channel and p-channel transistors, which allow solid HIGH and LOW
output levels without a pull-up resistor — good for logic levels.
Simpler architecture — only a single register and the I/O can be both input and output
at the same time. Totem pole I/O have a direction register that specifies the port pin
direction and it is always in that configuration unless the direction is explicitly
changed.
Does not require a command byte. The simplicity of one register (no need for the
pointer register or, technically, the command byte) is an advantage in some
embedded systems where every byte counts because of memory or bandwidth
limitations.
If more than 2 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the
master generates a ‘no acknowledge’.
Fig 11. Device ID field reading PCA9672
002aac327
A6 A5 A4 A3 A2 A1 A0
I2C-bus slave address
of the device to be identified
A
no acknowledge
from master
P
STOP condition
M
11
M
10
M9 M8 M7 M6 M5 M4
Sr
repeated START
condition
1 A
R/W
S
1
0
Device ID address
START condition
0 A
R/W
acknowledge from
one or several slaves
0 A
don’t care
acknowledge from
slave to be identified
1
0
Device ID address
acknowledge from
slave to be identified
A M3 M2 M1 M0
acknowledge
from master
manufacturer name = 000000000000
P8 P7 P6 P5 A
acknowledge
from master
P4 P3 P2 P1 P0 R2 R1 R0
part identification = 001000011
revision = 000
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