參數(shù)資料
型號(hào)： PCA9672D,512
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 4/36頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 8B 16SOIC
標(biāo)準(zhǔn)包裝： 48
接口： I²C
輸入/輸出數(shù)： 8
中斷輸出： 是
頻率 - 時(shí)鐘： 1MHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SO
包裝： 管件
包括： POR
其它名稱(chēng)： 935282746512
PCA9672D
PCA9672D-ND
PCA9672
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 27 May 2013
12 of 36
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset
8.3 Reading from a port (Input mode)
The port must have been previously written to logic 1, which is the condition after
power-on reset or hardware reset or software reset. To enter the Read mode, the master
(microcontroller) addresses the slave device and sets the last bit of the address byte to
logic 1 (address byte read). The slave will acknowledge and then send the data byte to
the master. The master will NACK and then send the STOP condition or ACK and read the
input register again.
The read of any pin being used as an output will indicate HIGH or LOW depending on the
actual state of the input pin.
If the data on the input port changes faster than the master can read, this data may be
lost. The DATA 2 and DATA 3 are lost because these data did not meet the set-up time
and hold time (see Figure 14).
Simple code for Read cycle:
<S> <slave address + R> <ACK> <DATA in> <ACK> <DATA in> ... <NACK> <P>
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9672 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9672 registers and I2C-bus/SMBus state machine will initialize to their default
states of all I/Os to inputs with weak current source to VDD. Thereafter VDD must be
lowered below VPOR and back up to the operation voltage for power-on reset cycle.
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at
any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode). Input
data is lost.
Fig 14. Read input port register
A5 A4 A3 A2 A1 A0
1
A
SA6
slave address
START condition
R/W
acknowledge
from slave
002aah383
data from port
A
acknowledge
from master
SDA
1
no acknowledge
from master
read from
port
data at
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
tv(INT)
trst(INT)
th(D)
tsu(D)
trst(INT)
DATA 1
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