參數(shù)資料
型號: PCA9674ABS
廠商: NXP Semiconductors N.V.
元件分類: I2C/I2S
英文描述: Remote 8-bit I-O expander for Fm+ I2C-bus with interrupt
封裝: PCA9674ABS<SOT758-1 (HVQFN16)|<<http://www.nxp.com/packages/SOT758-1.html<1<Always Pb-free,;PCA9674AD<SOT162-1 (SO16)|<<http://www.nxp.com/packages/SOT162-1.html<1<
文件頁數(shù): 14/32頁
文件大?。?/td> 299K
代理商: PCA9674ABS
PCA9674_PCA9674A
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 29 September 2011
14 of 32
NXP Semiconductors
PCA9674; PCA9674A
Remote 8-bit I/O expander for Fm+ I
2
C-bus with interrupt
8.3 Reading from a port (Input mode)
All ports programmed as input should be set to logic 1. To read, the master
(microcontroller) first addresses the slave device after it receives the interrupt. By setting
the last bit of the byte containing the slave address to logic 1 the Read mode is entered.
The data bytes that follow on the SDA are the values on the ports.
If the data on the input port changes faster than the master can read, this data may be
lost.
Fig 12. Write mode (output)
A5 A4 A3 A2 A1 A0
0
A
S A6
slave address
START condition
R/W
acknowledge
from slave
002aae524
P6
1
P7
data 1
A
acknowledge
from slave
1
2
3
4
5
6
7
8
SCL
9
SDA
A
acknowledge
from slave
write to port
data output from port
t
v(Q)
DATA 2 VALID
P5
data 2
P4 P3 P2 P1 P0
P7
P4 P3 P2 P1 P0
P6
P5
0
t
v(Q)
DATA 1 VALID
P5 output voltage
I
trt(pu)
I
OH
P5 pull-up output current
t
d(rst)
INT
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at
any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode). Input
data is lost.
Fig 13. Read input port register
A5 A4 A3 A2 A1 A0
1
A
S A6
slave address
START condition
R/W
acknowledge
from slave
002aae525
data from port
A
acknowledge
from master
SDA
1
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
t
v(D)
t
d(rst)
t
h(D)
t
su(D)
t
d(rst)
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